1. Field of the Invention
The present invention provides a circuit for the detection of changes of address when a word line in a memory is being addressed. It relates particularly to memories whose memory cells comprise floating-gate transistors acting as storage elements. The programming of these cells is generally performed either by generating a saturation current or by creating an electrical field effect in this floating-gate transistor. Such memories include EPROM or EEPROM type memories. However, the invention may be applied to other types of memory. One particular feature of the invention is that it deals with the problems that arise on a data bus during a long period of writing, namely during programming or erasure periods.
2. Discussion of the Related Art
In the case of EEPROM type memories, each information storage element or memory cell consists of a floating-gate transistor. This type of transistor may have two states. Thus, in the case of an N channel MOS transistor, in a first state, either no charge or a positive charge is trapped at the floating gate. A conduction channel may exist between the source and the drain. The transistor is then conductive and behaves like a closed switch. In a second state, electrons are trapped at the floating gate. They therefore prevent the creation of a conduction channel in the substrate between the source and the drain. In this case, the transistor is off and behaves like an open switch.
The programming of the floating-gate transistor of an EEPROM type memory cell is obtained by subjecting the drain and source regions of this transistor to a potential that has a higher value compared with the potential to which the control gate of this transistor, superimposed on the floating gate, is subjected. The programming therefore requires that at least one of the drain and source regions should be subjected to a high voltage VPP.
A particular application of the invention is that of programming in page mode. In such a mode, the programming of several memory cells connected to one and the same word line of the memory array is done at the same time. This mode of programming is very useful for it enables access to several memory cells of the memory array at the same time. Indeed, rather than performing the programming of the memory cells one after the other, in order to reduce the programming time, inasmuch as the cells are distributed at the intersections of bit lines and word lines, it is preferable firstly to select a set of bit lines and, secondly, to select a word line for the programming at the same time of all the memory cells belonging to these bit lines and to this word line. Then the word line may be changed to access a new set of memory cells belonging to these bit lines and to this new word line.
The programming, in page mode, of cells of an EEPROM type memory is done in several steps. Firstly, the selection of the bit lines is neutralized and, during this neutralization, all the bit lines are precharged at a high potential. Then, the bit lines are selected by selectively eliminating the neutralization. Finally, for the programming of the memory cells, a zero potential is imposed on the control gates of the floating-gate transistors of the memory cells to be programmed. Thus, only the selected transistors get programmed. It must be noted that these selected transistors have not been programmed during the precharging because, at this time, the transistors providing access to these cells are off. The transistors are turned off by a command applied to their control gate.
However, this precharging of the bit lines lasts long enough for it to be possible to prompt a change in the address of a word line. This change may arise out of any cause such as a parasite or a control error. The circuits proposed in the prior art naturally take account of this change of address. Thus, a programming or erasure of the cells is done on a word line that is different from the word line selected beforehand by the user.